1. Field of the Invention
The present invention relates to an error generating apparatus for a solid state drive tester. In more particularly, the present invention relates to an error generating apparatus for a solid state drive tester, capable of testing an error processing operation of a storage by inserting errors into a specific instruction to be transmitted to the storage and detecting the results of the error processing operation of the storage when testing the storage.
2. Description of the Related Art
Until now, hard disk drives (HDDs) have been most generally known in the art and used as large capacity digital media storage devices. However, recently, as prices of NAND flash semiconductor devices, which can store large data and have a characteristic in which data stored therein are not erased in the power-off state, among semiconductor devices having a memory function are lowered, the large capacity digital media storage apparatus such as solid state drives (SSDs) based on a semiconductor having a memory function are newly appearing.
The SSD represents the writing/reading rate that is three times to five times faster than that of existing HDDs, and has the performance superior to that of the HDDs in that the reading/writing rate for a random address required by a database management system is several hundreds of times faster than that of the HDDs. In addition, since the SSD is operated in a silent way, a noise problem of an existing hard disk can be solved. Further, since the SSD is operated with power consumption significantly lower than that of the HDD, the SSD is known as to most suitable for a digital device, such as a laptop computer, which requires low power consumption.
In addition, the SSD has durability against an external impact stronger than that of the HDD, and the SSD can be manufactured in the smaller and more various shapes as compared with the HDD having a formulaic shape in terms of an external design. Accordingly, the external shape of an electronic product employing the SSD can be made smaller, so that the SSD represents many excellent advantages in the applications thereof.
Due to the advantages, it is expected that the distribution of SSDs can be expanded to searches, home shopping, storage media of video service servers, storage media for storing various R&D materials, and special equipment, as well as existing desktop computers or laptop computers in the future.
In order to test the SSD, an SSD tester according to the related art is disclosed in FIG. 1.
The SSD tester according to the related art as shown in FIG. 1 includes a host terminal 110, a network 120, a test control unit 130, and a memory 140. In FIG. 1, reference numeral 200 denotes a storage unit 200 including a plurality of storages 201 to 200+N which are test targets which are test targets.
The host terminal 110 functions to receive a test condition for storage test from a user, and the network 120 is in charge of a data interface between the host terminal 110 and the test control unit 130.
The memory 140 has a program embedded therein to test the SSD, and acts as a data storage device to store pattern data used for generating test patterns and data which are generated when testing the SSD.
The test control unit 130 tests a storage using a test pattern by adaptively selecting an interface according an interface type of the storage after generating the test pattern according to test conditions or randomly. In this case, preferably, a plurality of devices provided in the test control unit 130 to test the SSD are implemented in the form of one chip by using a field programmable gate array (FPGA).
More preferably, the test control unit 130 is divided into a control unit, which controls the test of the storage, and a test executing unit, which actually performs a test function, in hardware, so that a plurality of storages can be tested in real time.
The test control unit 130 includes a communication interface unit 131 connected to the host terminal 110 through the network 120 to receive user information and to transmit the test result to the host terminal 110, a storage interface unit 132 for interfacing the storage unit 200, and an embedded processor 133 for controlling storage test, and a test executing unit 160 which is connected to the embedded processor 133, generates test patterns for storage test to transmit the test patterns to a storage, and reads the test patterns out of the storage and compares the test patterns of the storage with the generated test patterns to determine the failure state of the storage test.
In addition, as shown in FIG. 2, the test executing unit 160 includes a pattern data generator 161, which generates pattern data by selecting one of pattern data generated under the test conditions and randomly-generated pattern data according to a pattern data selection signal output from the embedded processor 133, a buffer memory 162, which temporarily stores data read out of the storage, a failure processor 163, which compares the pattern data generated from the pattern data generator 161 with the read data temporarily stored in the buffer memory 162 to determine a failure, and generates failure information in case of a failure, a failure memory 164, which stores the failure information generated from the failure processor 163, and an instruction generator 165 which transmits a test instruction generated from the embedded processor 133 to the storage interface unit 132.
In addition, the storage interface unit 132 includes a plurality of multi-interfaces 151 to 151+N used to simultaneously test a plurality of storages. Hereinafter, since the multi-interface 151 has the same internal structure and operation, only one multi-interface 151 will be representatively described for the convenience of the explanation.
As shown in FIG. 3, the multi-interface 151 includes an advanced host controller interface (AHCI) unit 151a for interfacing instruction data generated in the embedded processor 133, a direct memory access (DMA) unit 151b for interfacing writing data generated in the embedded processor 133, a serial-ATA (SATA) interface unit 151c for supporting an SATA interface between the AHCI unit 151a and the storage 201, and between the DMA unit 151b and the storage 201, a serial attached SCSI (SAS) interface unit 151d for supporting an SAS interface between the advanced host controller interface 151a and the storage 201 and between the direct memory access unit 151b and the storage 201, a PCI express (PCIe) interface unit 151e for supporting a PCIe interface between the AHCI unit 151a and the storage 201 and between the DMA unit 151b and the storage 201, and a multiplexer (MUX) 151f for selecting one of the SATA interface unit 151c, the SAS interface unit 151d, and the PCIe interface unit 151e according to an interface selection signal generated from the embedded processor 133 to connect the storage 201 and the embedded processor 133.
In the state that the test devices of the SDD having the above structure are provided in the form of one chip on one board through the FPGA, a user connects the SSD tester to a storage to be tested, inputs test condition through the host terminal 110, and then inputs a macro instruction used to test the storage through the host terminal 110 in order to test the SSD. The test condition may include an interface selection signal for the interface with the storage to be tested, and a test pattern selection signal. The test pattern selection signal is used to determine if preset pattern data are selected or if randomly-generated pattern data are selected.
The test condition and the macro instruction input by the user through the host terminal 110 are transferred to the test control unit 130 prepared in the form of one chip through the network 120.
The communication interface unit 131 of the test control unit 130 receives the test condition and the macro instruction, which are input by the user through the network 120, and transmits the test condition and the macro instruction to the embedded processor 133. If the test condition is input by the user and a storage test is requested, the embedded processor 133 extracts a test program for the storage test from the memory 140 to start the storage test. In this case, as an initial operation of the test, the embedded processor 133 extracts test pattern data corresponding to the test condition input by the user from the memory 140 and transmits the test pattern data to the test executing unit 160.
The test executing unit 160 is prepared by realizing a module for actually performing a test in the form of a logic separated from the embedded processor 133. As described above, the load of the embedded processor 133 can be reduced by separating the module for performing the test (generating test pattern data and determining failure) from the embedded processor 133. Accordingly, a plurality of storages can be simultaneously controlled and tested, so that the whole test time can be reduced.
In more detail, as shown in FIG. 2, the pattern data generator 161 of the test executing unit 160 generates pattern data by selecting one of pattern data generated corresponding to the test conditions and randomly-generated pattern data according to the pattern data selection signal output from the embedded processor 133.
The pattern data are transmitted to the multi-interface 151 of the storage interface unit 132. In addition, the instruction data output from the embedded processor 133 to perform the storage test are transmitted to the multi-interface 151 after passing through the instruction generator 165.
The multi-interface 151 selects an interface corresponding to the storage 201 according to the interface selection signal output from the embedded processor 133, transforms the pattern data and the test instruction in the form suitable for the selected interface, and transmits the pattern data and the test instruction to the storage 201.
In this case, as shown in FIG. 3, an interface selection signal is provided to the multi-interface 151 so that the interface corresponding to the storage 201 may be selected.
For example, the interface selection signal is applied to the multiplexer 151f of the multi-interface 151 from the embedded processor 133, and the multiplexer 151f selects one of the interfaces (SATA, SAS, and PCIe) according to the interface selection signal. In other words, the multiplexer 151f selects an interface corresponding to the interface of the storage 201.
In other words, the instruction data for the storage test output from the embedded processor 133 are input to the SATA interface unit 151c, the SAS interface unit 151d, and the PCIe interface unit 151e through the instruction generator 165 and the AHCI unit 151a. 
The writing data (test patterns) output from the pattern data generator 161 of the test executing unit 160 are input to the SATA interface unit 151c, the SAS interface unit 151d, and the PCIe interface unit 151e respectively through the direct memory access (DMA) unit 151b. 
If the instruction data and the writing data are input to the interfaces in this way, the multiplexer 151f selects only one interface according to an interface selection signal. Thereafter, the selected interface unit transmits the input instruction data and the input writing data to the storage 201, so that the test for the storage 201 is started. For example, when the storage 201 employs an SATA interface, the SATA interface unit 151c is selected, so that the instruction data and writing data input to the SATA interface 151c are transformed into a format suitable for the SATA interface and applied to the storage 201.
In this case, since the SATA interface, the SAS interface, and the PCIe interface employ standard interfaces, the details thereof will be omitted.
After the writing data and the instruction data have been transmitted to the storage 201, if the test of the storage 201 is started, the result data for the test of the storage 201 are readout in response to a read instruction, and the readout data are transmitted to the test executing unit 160 after sequentially passing through the multi-interface 151 and the embedded processor 133.
The buffer memory 162 of the test executing unit 160 temporarily stores the readout data. If the readout data have been completely stored, the failure processor 163 compares expectation data (pattern data) output from the pattern data generator 161 with the readout data received from the embedded processor 133 according to channels by using a comparator embedded therein. If the expectation data are the same as the read data, the failure processor 163 does not output the result. If the expectation data differ from the read data, the failure processor 163 generates a failure signal.
An internal failure counter increases an internal failure count value by 1 based on the failure signal and outputs the internal count value, and an internal failure memory address generator generates a failure memory address to be transmitted to the failure memory 164.
The failure memory 164 uses the internal failure memory address into a logical block address (LBA) and stores the expectation data and the readout data input into the failure processor 163 as failure information.
The failure of the storage test is not processed in the embedded processor 133, but processed in the test executing unit 160 realized in the form of a logic separated from the embedded processor 133. If necessary, a plurality of pattern data are simultaneously generated and the failure states of a plurality of storages are simultaneously determined. Accordingly, the load of the embedded processor 133 can be reduced. In addition, since the storages are simultaneously tested, the storage test time can be reduced.
In addition, the failure information stored in the failure memory 166 is transmitted to the embedded processor 133 according to the request of the embedded processor 133, and transmitted to the host terminal 110 through the communication interface unit 131 and the network 120.
Therefore, a user can easily recognize the test result of the storage through the host terminal 110.
However, according to the related art, since only normal data for a storage test are transmitted in order to test the storage, various characteristics of the storage cannot be tested.
In other words, error data and instructions cannot be transmitted to the storage, and the error processing of the storage cannot be tested.
In addition, when the storage is tested, various types of errors cannot be generated. Accordingly, various characteristics, such as the operation of the storage against errors and an error processing operation of the storage, cannot be tested.